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07/28/2023
VeriGen: A Large Language Model for Verilog Code Generation
In this study, we explore the capability of Large Language Models (LLMs)...
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06/24/2023
LLM-assisted Generation of Hardware Assertions
The security of computer systems typically relies on a hardware root of ...
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02/02/2023
Fixing Hardware Security Bugs with Large Language Models
Novel AI-based code-writing Large Language Models (LLMs) such as OpenAI'...
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12/23/2022
Security and Interpretability in Automotive Systems
The lack of any sender authentication mechanism in place makes CAN (Cont...
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12/13/2022
Benchmarking Large Language Models for Automated Verilog RTL Code Generation
Automating hardware design could obviate a significant amount of human e...
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06/16/2020
A generalizable saliency map-based interpretation of model outcome
One of the significant challenges of deep neural networks is that the co...
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06/12/2020